Technical Publications in the field of signal processing, Image processing, digital filtering, harmonic measurement and embedded design are sorted here. You can download it for research purposes.
Embedded Design of Novel Edge Detection Algorithm for Optic zForce Air Touch Solution
Confidential Internal use only
A proximity sensor including a housing, light emitters mounted in the housing for projecting light out of the housing along a detection plane, light detectors mounted in the housing for detecting amounts of light entering the housing along the detection plane, whereby for each emitter-detector pair (E, D), when an object is located at a target position p(E, D) in the detection plane, corresponding to the pair (E, D), then the light emitted by emitter E is scattered by the object and is expected to be maximally detected by detector D, and a processor to synchronously activate emitter-detector pairs, to read the detected amounts of light from the detectors, and to calculate a location of the object in the detection plane from the detected amounts of light, in accordance with a detection-location relationship that relates detections from emitter-detector pairs to object locations between neighboring target positions in the detection plane.
High linear low noise amplifier based on self-biasing multiple gated transistors
International conference on electrical, electronics and system engineering (iceese2014) Malaysia, pp1-4, DOI: 10.1109/ICEESE.2014.7154594
Noise level frequently set the basic limit on the smallest signal. New noise reduction technology and amplifiers voltage-noise density, yet still offer high speed, high accuracy, and low power solution. Low noise amplifiers always play a significant role in RF technology. Hence in this paper, high linear low noise amplifier (LNA) using cascode self-biased multiple gated transistors (MGTR) is presented. The proposed system is covering 0.9 to 2.4 GHz applications. To verify the functionality of the proposed LNA as a bottleneck of RF technology, a cascode LNA without MGTR is implemented and synthesized. The
comparison has been done with the single-gate LNA. From the synthesized result, proposed LNA obtained 10 dBm third-order input intercept point (IIP3) in compare with single-gate LNA at 9
dB gain. The proposed LNA is implemented in 90 nm CMOS technology and reported 13 dBm IIP3, 1.9 dB NF and 9 dB gain while consuming 7.9 mW from 2 V supply.
Highly linear low-pass Gm − C filter with self-biasing transconductor for digital TV tuner
International Journal of Electronics Letters (ISI Indexed) Taylor and Francis. pp: 1-10. DOI:10.1080/00207217.2013.780264
To improve the linearity of the transconductor in digital TV tuner application, a new technique of multiple gated transistors in self-biasing basis is presented. The proposed design decreases the bill-of-material (BOM) and offers less complexity of the structure. In addition, the proposed transconductor with utilizing by third-order Chebyshev introduces low-pass filter with low power consumption and the cutoff frequency of 50-200 MHz. The hybrid tracking low-pass filter is designed to overcome the issue of local oscillator harmonic-mixing for Advanced Television System Committee terrestrial digital TV tuner integrated circuit. The proposed operational transconductor amplifier (OTA) is designed and implemented in 90 nm CMOS technology. The simulation result with the two-tone test at 100 MHz center frequency proves the proposed OTA has 5 dBm Input-referred Third-Order Intercept Point (IIP3) in compare with
a single-gate OTA in the third-order Chebyshev filter. The proposed OTA achieves maximum noise figure (NF) of 13 dB and maximum IIP3 of approximately 21.7 dBm at 100 MHz, whereas consuming 18 mA with 1.2 V supply voltage and it shows great improvement.
Novel Architecture of Smart FFT Processor
ISBN 978-3-659-61152-0, Lambert Academic Publishing, Germany, 2014
Electrical motors are vital components of many industrial processes and their operation failure can lead to loss in production. Motors are found in many applications in industrial apparatus. Conditioned monitoring of the motor enables early detection of abnormalities; for proactive response maintenance procedures to avoid catastrophe. The diagnosis of motor faults improves the efficiency of industrial plants. Meanwhile the precise analysis and accurate measurement of harmonic provides a reliable scientific industrial application. Hence, the high performance DSP processor is the important method of electrical harmonic analysis. However, it can be realized in embedded systems. In this book, the effort was taken to implement a novel high-resolution single chip 1024-point FFT processor architecture for improvement of the harmonic measurement techniques. This book starts with design then followed by the simulation and its hardware implementation to demonstrate the benefit that is achieved by the proposed 1024-point FFT processor.
Advanced Frequency Identification Power Metering System for Energy Usage
IEEE International Conference on Smart Instrumentation, Measurement and Applications. Malaysia
Energy meter measures the amount of power consumed by electrical loads in residential, industrial and commercial applications. In this project, the focus goes to the implementation of a smart power measurement system to allocate identification for individuals and determine the client’s energy usage. The incorporation of two PIC 16F877A microcontrollers and radio-frequency identification (RFID)
reader in this research work make the system operation smooth and reliable. This paper presents the development of an intelligent prepaid power metering system enabling power utilities to collect electricity bills from consumers prior to the usage of power. Homeowners are able to monitor reliable power consumption data for efficient power management. To conclude, a graphical user interface (GUI) has been designed to be applied for data transmission between the personal computer and RFID a smart card which allows the credit to be transferred to the smart card.emonstrate the benefit that is achieved by the proposed 1024-point FFT processor.
VLSI Design Of Advanced Digital Filters
ISBN 978-3-659-40080-3, Lambert Academic Publishing, Germany
The Cascaded Integrator Comb filters (CIC) find many applications in recent electronic devices such as frequency selection functions in a digital radio or modem and any filter structure that is required to efficiently process large sample rate factor. These filters are normally located after the sigma-delta modulator and have a regular structure. These types of filters do not require multipliers and the coefficient storage unlike in the normal digital FIR and IIR filters because of all filter coefficients are unity. Hence, it can be efficiently implemented to operate at high speed. Hence, this book describes the Very Large Scale Integration (VLSI) implementation of the CIC filters that are suitable for high-performance audio applications.
RFID-BASED Prepaid Power Meter
IEEE Conference On Research and Development (Scored) IEEE; 2013, 978-1-4799-3656-5/13-pp
An Electric power meter is an important component in electric energy service. In the past, many consumers have complained about reading inaccurate of the electric meter. This research presents the development of an electrical power meter equipped with RFID reader. The RFID reader reads a valid RFID card and activates the power meter so that it can supply electricity. When the credit is about low or before the electricity is auto cut off, an SMS message will be sent to the user’s handphone to alert.
Adaptive Intelligent Spider Robot
IEEE Conference on Systems, Process and Control (ICSPC 2013),
DOI: 10.1109/SPC.2013.6735153 , Page(s): 310 - 315 978-1-4799-2209-3/13, pp: 310-315
This paper presents the development of an adaptive intelligent spider robot. With the incorporation of sensors, the four-legged spider robot is able to monitor the environment wirelessly. A new auto-station adaptation National Instrument (NI) controller in the application for an intelligent robot is proposed. The research work will solve the weak adaptive ability of conventional existing robot. The proposed project proposes a self-adaptive smart spider robot that functions without human interfacing. The proposed design utilizes the control scheme with National Instruments (NI) LabVIEW to produce a smart portable system. Furthermore, the adaptive intelligent spider robot easily adapts to new situations when facing obstacles. The design is carried out using feedback loop schematic LabVIEW interfacing with the smart controller and incorporation of GH-311 Ultrasonic Sensor to detect any obstacle in front of the robot, GH-312 Smoke Sensor which use to detect smoke in the particular area and LM35 Temperature sensor to get the temperature for the surround. The proposed module was designed and implemented using movable wireless Router Module TP-Link TL-MR3420 Router transceiver for device communication. The robot was tested and analyzed showing the system efficiency of above 95%, which is competent in robotic applications [1-4]..
Design an Advance computer-aided tool for Image Authentication and Classification
American Journal of Applied Sciences, (ISI Index. doi:10.3844/ajassp.2013.696.705 Published Online 10 (7): 696-705. ISSN: 1546-9239
Over the years, advancements in the fields of digital image processing and artificial intelligence have been applied in solving many real-life problems. This could be seen in facial image recognition for security systems, identity registrations. Hence a bottleneck of identity registration is image processing. These are carried out in form of image preprocessing, image region extraction by cropping, feature extraction using Principal Component Analysis (PCA) and image compression using Discrete Cosine Transform (DCT). Other processing includes filtering and histogram equalization using contrast stretching is performed while enhancing the image as part of the analytical tool. Hence, this research work presents a universal integration image forgery detection analysis tool with image facial recognition using Back Propagation Neural Network (BPNN) processor. The proposed designed tool is a multi-function smart tool with the novel architecture of programmable error goal and light intensity. Furthermore, its advance dual database increases the efficiency of a high-performance application. With the fact that, the facial image recognition will always, give a matching output or closest possible output image for every input image irrespective of the authenticity, the universal smart GUI tool is proposed and designed to perform image forgery detection with the high accuracy of ±2% error rate. Meanwhile, a novel structure that provides efficient automatic image forgery detection for all input test images for the BPNN recognition is presented. Hence, an input image will be authenticated before being fed into the recognition tool.
Smart Analytical Signature Verification For DSP Applications
IEEE Conference on Systems, Process and Control (ICSPC 2013), DOI: 10.1109/SPC.2013.6735151 Page(s): 301 – 305
Signature verification is an authentication technique that considers handwritten signature as a “biometric”. From a biometric perspective, this project made use of automatic means through an integration of intelligent algorithms to perform signal enhancement function such as filtering and smoothing for optimization in conventional biometric systems. A handwritten signature is a 1-D Daubechies wavelet signal (db4) that utilizes Discrete Wavelet Transform (DWT) and Discrete Cosine Transform (DCT) collectively to create a feature dataset with d-dimensional space. In the proposed work, the statistical features characteristics are extracted from each particular signature per data source. Two databases called Signature Verification Competition (SVC) 2004 database and SUBCORPUS-100 MCYT Bimodal database are used to cooperate with the design algorithm. Furthermore, dimension reduction technique is applied to the large feature vectors. A system model is trained and evaluated using the support vector machine (SVM) classifier algorithm. Hence, an equal error rate (EER) of 8.7% and an average correct verification rate of 91.3%
Smart GSM Based Home Automation System
IEEE Conference on Systems, Process and Control (ICSPC 2013), DOI: 10.1109/SPC.2013.6735152 Page(s): 306 – 309
This research work investigates the potential of ‘Full Home Control’, which is the aim of the Home Automation Systems in near future. The analysis and implementation of the home automation technology using Global System for Mobile Communication (GSM) modem to control home appliances such as light, conditional system, and security system via Short Message Service (SMS) text messages is presented in this paper. The proposed research work is focused on the functionality of the GSM protocol, which allows the user to control the target system away from residential using the frequency bandwidths. The concept of serial communication and AT-commands has been applied towards the development of the smart GSM-based home automation system. Homeowners will be able to receive feedback status of any home appliances under control whether switched on or off remotely from their mobile phones. PIC16F887 microcontroller with the integration of GSM provides the smart automated house system with the desired baud rate of 9600 bps. The proposed prototype of GSM based home automation system was implemented and tested with a maximum of four loads and shows the accuracy of ≥98%.
Static Quantized Radix-2 FFT/IFFT Processor for Constraints Analysis
International Journal of Electronics Taylor and Francis. Pp: 1-10. DOI:10.1080/00207217.2013.780264
This article may be used for research, teaching, and private study purposes. Any substantial or systematic reproduction, redistribution, reselling, loan, sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. The publisher does not give any warranty express or implied or make any representation that the contents will be complete or accurate or up to date. The accuracy of anyinstructions, formula, and drug doses should be independently verified with primary sources. The publisher shall not be reliable for any loss, actions, claims, proceedings, demand, or costs or damages whatsoever or howsoever caused arising directly or
indirectly in connection with or arising out of the use of this material.
Universal Computer aided design for electrical machines
IEEE 8th International colloquium on signal Processing Applications conference (CSPA 2012). pp: 99-104. DOI: 10.1109/CSPA.2012.6194699
Electrical machines are devices that change either mechanical or electrical energy to the other and also can alternate the voltage levels of an alternating current. The need for electrical machines cannot be overemphasized since they are used in various applications in the world today. Its design is to meet the specifications as stated by the user and this design has to be an economical one. The design, therefore, revolves around designing the machine to meet the stipulated performance required, the cost available and the lasting life of the machine. This work aims to eliminate the tediousness involved in the manual hand calculations of designing the machines by making use of a graphical user interface and using iterations in situations where the data would have been assumed.
Characteristic Analysis of 1024-Point Quantized Radix-2 FFT/IFFT Processor
IEEE-ICSE2012 Proc.International Conference on Semiconductor Electronics (ICSE-2012). Pp 664-668.DOI: 10.1109/SMElec.2012.6417231 . ISBN: 978-1-4673-2395-6
The precise analysis and accurate measurement of harmonic provides a reliable scientific industrial application. However, the high-performance DSP processor is the important method of electrical harmonic analysis. Hence, in this research work, the effort was taken to design a novel high-resolution single 1024-point fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) processors for improvement of the harmonic measurement techniques. Meanwhile, the project is started with design and simulation to demonstrate the benefit that is achieved by the proposed 1024-point FFT/IFFT processor. The pipelined structure is incorporated in order to enhance the system efficiency. As such, a pipelined architecture was proposed to statically scale the resolution of the processor to suite adequate trade-off constraints. The proposed FFT makes use of programmable fixed-point/floating-point to realize higher precision FFT.
Mathematical Toolbox and its application in the Development of Laboratory Scale Vertical Axis Wind Turbine
2012 IEEE International Conference on Power and Energy Dec2012 - PECON. pp. 99-104. DOI: 10.1109/PECon.2012.6450362 . ISBN: 978-1-4673-5017-4
A wind turbine works with the principle of extracting energy from the wind to generate electricity. The power generated is directly proportional to the wind speed available. There are two major types of wind turbine design namely the horizontal and vertical axis wind turbine depending on the orientation of the turbine rotor and its generator. This paper deals with the design of vertical turbine due to its advantage of operating at a low wind speed over that of the horizontal turbine. The analysis of change in the parameters of a vertical axis wind turbine is investigated to get the optimized way in which the rotor of the turbine is to be designed. This is done through modeling and simulation of the turbine using various parameters in the MATLAB/SIMULINK environment. A graphical user interface is created for a generic model of vertical axis wind turbine that is used to determine its parameters.
Novel Architecture of Pipeline Radix 2 power of 2 SDF FFT Based on Digit-Slicing Technique
IEEE-ICSE2012 Proc.International Conference on Semiconductor Electronics (ICSE-2012). Pp 470-474. DOI: 10.1109/SMElec.2012.6417188 ISBN: 978-1-4673-2395-6
The prevalent need for very high-speed digital signals processing in wireless communications has driven the communications system to high-performance levels. The objective of this paper is to propose a novel structure for efficient implementation for the Fast Fourier Transform (FFT) processor to meet the requirement for high-speed wireless communication system standards. Based on the algorithm, architecture analysis, the design of pipeline Radix 2power of 2 SDF FFT processor based on digit-slicing Multiplier-Less is proposed. Furthermore, this paper proposed an optimal constant multiplication arithmetic design to multiply a fixed point input selectively by one of the several present twiddle factor constants. The proposed architecture was simulated using MATLAB software and the Field Programmable Gate Array (FPGA) Virtex 4 was targeted to synthesis the proposed architecture. The design was tested in real hardware of TLA5201 logic analyzer and the ISE synthesis report results the high speed of 669.277 MHz with the total equivalent gate count of 14,854. Meanwhile, It can be found as significant improvement over Radix 22 DIF SDF FFT processor and can be concluded that the proposed pipeline Radix 22 DIF SDF FFT processor based on digit-slicing multiplier-less is an enable in solving problems that affect the most high-speed wireless communication systems capability in FFT and possesses huge potentials for future related works and research areas.
Planar Dipole Antenna Design At 1800MHz Band Using Different Feeding Methods For GSM Application
IEEE-ICSE2012 Proc.International Conference on Semiconductor Electronics (ICSE-2012). Pp 560-564. DOI: 10.1109/SMElec.2012.6417208 . ISBN: 978-1-4673-2395-6
This research work focuses on the design and simulation of a planar dipole antenna for 1800MHZ Band for Global System Mobile GSM application using Computer Software Technology CST studio software. The antenna is structured on a fire resistance FR4 substrate with a relative constant of 4.3 S/m. Two types of feeding configuration are designed to feed the antenna in order to match 50 Ω transmission lines which are via-hole integrated balun and quarter wavelength open stub. The via-hole is capable to provide maximum return loss of -25dB, bandwidth of 18.4% and the voltage standing wave ratio (VSWR) of 1.116 V at optimum dimension of length 59mm and width 4mm; the bandwidth is improved 25% to 30% by extending the width of the antenna 8 mm to 10 mm followed by deterioration of return loss value to - 15dB. While the open stub at length of 67 mm, the width of 6 mm and height 1.6mm will provide max return loss of -47.88dB and bandwidth of 17% with VSWR 1.008 << 2. The way that the antenna substrate has influenced the performance of the antenna. The lower relative constant will result in the higher return lows, narrower bandwidth and better radiation pattern in trade-off the resonant length Via-hole and then the quarter wave open stub are most convenient for practical implementation.
Smart Novel Computer-based Analytical Tool for Image Forgery Authentication
IEEE Circuit and Systems (CAS) Conference. Pp.120-125. DOI: 10.1109/ICCircuitsAndSystems.2012.6408276. ISBN: 978-1-4673-3117-
This paper presents an integration of image forgery detection with image facial recognition using black propagation neural network (BPNN). We observed that facial image recognition by itself will always give a matching output or closest possible output image for every input image irrespective of the authenticity or otherwise not of the testing input image. Based on this, we are proposing the combination of the blind but powerful automation image forgery detection for entire input images for the BPNN recognition program. Hence, an input image must first be authenticated before being fed into the recognition program. Thus, an image security identification and authentication requirement, any image that fails the authentication/verification stage are not to be used as an input/test image. In addition, the universal smart GUI tool is proposed and designed to perform image forgery detection with the high accuracy of ±2% error rate.
FPGA Implementation of pipeline Digit-Slicing Multiplier-Less Radix 2 power of 2 DIF SDF Butterfly for Fourier Transform Structure
European Conference on Antennas and Propagation (EUCAP2011). Pp 4168- 4172.
The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This paper presents FPGA implementation of pipeline digit-slicing multiplier-less radix 22 DIF (Decimation In Frequency) SDF (single path delay feedback) butterfly for FFT structure. The approach is taken; in order to reduce computation complexity in butterfly multiplier, the digit-slicing multiplier-less technique was utilized in the critical path of pipeline Radix-22 DIF SDF FFT structure. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The multiplier input data was sliced into four blocks each one with four bits to process at the same time in parallel. The new architecture was investigated and simulated with MATLAB software. The Verilog HDL code in Xilinx ISE environment was derived to describe the FFT Butterfly functionality and was downloaded to Virtex II FPGA board. Consequently, the Virtex-II FG456 Proto board was used to implement and test the design on the real hardware. As a result, from the findings, the synthesis report indicates the maximum clock frequency of 555.75 MHz with the total equivalent gate count of 32,146 is a marked and significant improvement over Radix 22 DIF SDF FFT butterfly. In comparison with the conventional butterfly architecture design which can only run at a maximum clock frequency of 200.102 MHz and the conventional multiplier can only run at a maximum clock frequency of 221.140 MHz, the proposed system exhibits better results. It can be concluded that on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure is an enabler in solving problems that affect communications capability in FFT and possesses huge potentials for future related works and research areas.
Optimised Toolbox for the design of Rotary Reluctance Motors
IEEE Conference on Sustainable Utilization and Development in Engineering and Technology. pp 1-6. DOI: 10.1109/STUDENT.2011.6089318
Operation of the rotary reluctance machine is highly affected due to the sequential attraction-repulsion principle of the adjacent phase excitation. The problem has been identified and addressed by various researchers in the past decades. The effective magnetic design is one way of minimizing the effect. However, it is tedious and time-consuming as the design procedure involve higher analytical derivation and calculations. This paper presents a simpler graphical user interface toolbox to use for the design of reluctance motors. The developed interface calculates the analytical values of the aligned, unaligned and intermediate inductance values so that the user can interpret the inductance and torque profile easily. A new analytical method called Cyclic Integration Method (CIM) is proposed and is used for the performance evaluation of the designed toolbox.
Design of Automatic Soil Humidity Control using Maximum Power Point Tracking Controller
IEEE Conference on Research and Development, SCOReD 2010. pp: 1-5. 978-14244-8648-9/10
The photovoltaic system uses the photovoltaic array as a source of electrical power for the direct conversion of the sun’s radiation to direct current without any environmental hazards. The main purpose of this research is to design a converter with Maximum Power Point Tracker (MPPT) algorithm for any typical application of soil humidity control. Using this setup the major energy from the solar panel is used for the control of soil humidity. The design of the converter with MPPT together with the soil humidity control logic is presented in this paper. Experimental testing of the designed controller is implemented and evaluated for performance under laboratory environment.
On-Chip Implementation of High Resolution High Speed Floating Point Adder/Subtractor with Reducing Mean Latency for OFDM
American Journal of Engineering and Applied Sciences. 3(1): 25-30. ISSN: 1941-7020. DOI: 10.3844/ajeassp.2010.25.30
Fast Fourier transform (FFT) is widely applied in OFDM trance-receiver communications system. Hence Efficient FFT algorithm is always considered. This paper proposed FPGA realization of high-resolution high-speed low latency floating point adder/subtractor for FFT in OFDM trance-receiver. The design was implemented for 32 bit pipelined adder/subtractor which satisfied IEEE-754 Standard for Floating-point Arithmetic. The design was focused on the trade-off between the latency and speed improvement as well as resolution and silicon area for the chip implementation. In order to reduce the critical path and decrease the latency, the novel structure was designed and investigated. Consequently, synthesis report indicated the latency of 4 clock cycles due to each stage operated within just one clock cycle. The unique structure of designed adder well thought out resulted in 6691 equivalent gate count and lead us to obtain low area on the chip. The synthesis Xilinx ISE software provided results representing the estimated area and delay for design when it is pipelined to various depths. The report shows the minimum delay of 3.592 ns or maximum frequency of 278.42 MHz
On-Chip Implementation of Pipeline Digit-Slicing Multiplier-Less Butterfly for Fast Fourier Transform Architecture
American Journal of Engineering and Applied Sciences. 3(4):757-764. ISSN 1941-7020 DOI: 10.3844/ajeassp.2010.757.764
The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This study presents an on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure. The approach is taken; in order to reduce computation complexity in the butterfly, digit-slicing multiplier-less single constant technique was utilized in the critical path of Radix-2 Decimation In Time (DIT) FFT structure. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The new architecture was investigated and simulated with MATLAB software. The Verilog HDL code in Xilinx ISE environment was derived to describe the FFT Butterfly functionality and was downloaded to Virtex II FPGA board. Consequently, the Virtex-II FG456 Proto board was used to implement and test the design on the real hardware. As a result, from the findings, the synthesis report indicates the maximum clock frequency of 549.75 MHz with the total equivalent gate count of 31,159 is a marked and significant improvement over Radix 2 FFT butterfly. In comparison with the conventional butterfly architecture, the design that can only run at a maximum clock frequency of 198.987 MHz and the conventional multiplier can only run at a maximum clock frequency of 220.160 MHz, the proposed system exhibits better results. The resulting maximum clock frequency increases by about 276.28% for the FFT butterfly and about 277.06% for the multiplier. It can be concluded that on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure is an enabler in solving problems that affect communications capability in FFT and possesses huge potentials for future related works and research areas.
The Effect of the Digit Slicing Architecture on the FFT Butterfly
IEEE International Conference on Information Science Signal Processing and their Application. ISSPA 2010. Malaysia. pp. 802-805
Most communications systems tend to achieve bandwidth, power and cost efficiencies to capable to describe modulation scheme. Hence for signal modulation, orthogonal frequency division multiplexing (OFDM) transceiver is introduced to cover communications demand in four generation. However high-performance Fast Fourier Transforms (FFT) as a main heart of OFDM acts beyond the view. In order to achieve capable FFT, design, and realization of its efficient internal structure is key issues of this research work. In this paper implementation of high-performance butterfly for FFT by applying digit slicing technique is presented. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The new architecture was investigated and simulated with the MATLAB software. The Verilog HDL code in Xilinx ISE environment was derived to describe the FFT Butterfly functionality and was downloaded to Virtex II FPGA board.
VLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless Receivers
American Journal of Engineering and Applied Sciences. 3(4):663-669. ISSN 1941-7020. DOI:10.3844/ajeassp.2010.663.669.
The need for high performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the Analog to Digital Converter (ADC) for wireless transceiver. This research work presented the design of the novel class of decimation and its VLSI implementation which was the sub-component in the over sampling technique. The design and realization of main unit of decimation stage that was the Cascaded Integrator Comb (CIC) filter, the associated half band filters and the droop correction are also designed. The Verilog HDL code in Xilinx ISE environment has been derived to describe the proposed advanced CIC filter properties. Consequently, Virtex-II FPGA board was used to implement and test the design on the real hardware. The ASIC design implementation was performed accordingly and resulted power and area measurement on chip core layout. The proposed design focused on the trade-off between the high speed and the low power consumption as well as the silicon area and high resolution for the chip implementation which satisfies wireless communication systems. The synthesis report illustrates the maximum clock frequency of 332 MHz with the active core area of 0.308×0.308 mm2. It can be concluded that VLSI implementation of proposed filter architecture is an enabler in solving problems that affect communication capability in DSP application.
VLSI Implementation of High Resolution High Speed Low Latency Pipeline Floating point Adder/Subtractor for FFT Applications
International Conference on NanoTech. pp: 327-331. ISSN: 9789834 492106.
This paper presents an on-chip implementation of high-speed low latency floating point adder /subtractor with high accuracy performance for FFT in OFDM transceiver. However, due to high performance and high resolution, the floating point adder is matched with power network applications as well. The design was implemented for 32-bit pipelined adder/subtractor which satisfied IEEE-754 Standard for floating -point Arithmetic. The design is focused on the trade-off between the latency and speed improvement as well as resolution and silicon area for the chip implementation. In order to reduce the critical path and decrease the latency, the novel structure was designed and investigated. Consequently, synthesis report indicating the latency of 4 clock cycles due to each stage operate within just one clock cycle. The unique structure of designed adder well thought out. The synthesis software provides results representing the estimated area and delays for design when it is pipelined to various depths.
On-Chip Implementation of High Speed and High Resolution Radix 2 FFT algorithm
International Conference on Intelligent and Advanced System ICIAS 2007 organized by IEEE. University Technology Petronas, Malaysia. ISBN: 978-1-4244-1355-3 pp. 1286 – 1288
A new on-chip implementation of Fast Fourier Transform (FFT) based on Radix 2 is presented. The pipeline and parallel approaches are combined to introduce a new high-speed FFT algorithm which increases resolution by using floating point calculations in its structures. The design has the merits of low complexity and high-speed performance. Furthermore, latency reduction is an important issue to implement the high-speed FFT on FPGA. The proposed FFT algorithm shows the latency of (N/2 log(2) N) + 11. Moreover, this algorithm has the advantage of low mean squared error (MSE) of 0.0001 which is preferable to Radix 2 FFT.
VLSI Implementation of High Speed and High Resolution FFT Algorithm Based on Radix 2 for DSP Application
IEEE Student Conference on Research and Development, SCOReD 2007. National University of Malaysia, ISBN: 978-1-4244-1470-3, pp.1-4
Using Fast Fourier Transform (FFT) is indispensable in most signal processing applications. Designing an appropriate algorithm for the implementation of FFT can be efficacious in digital signal processing. Sophisticated techniques such as pipelining and parallel calculations have potential impacts on VLSI implementation of FFT algorithm. Furthermore, a mathematics approach such as floating point calculation achieves higher precision. In this paper, an efficient algorithm for using parallel and pipelining methods is proposed to implement high speed and high-resolution FFT algorithm. Latency reduction is an important issue to implement the high-speed FFT on FPGA. The Proposed FFT algorithm shows the latency of 5131 clock pulse when N refers to 1024 points. The design has the mean squared error (MSE) of 0.0001 which is preferable to Radix 2 FFT.
An Enhancement of Decimation Process using Fast Cascaded Integrator Comb (CIC) Filter
IEEE International Conference on Semiconductor Electronics. Malaysia, pp. 811-815
The oversampling technique has been shown to increase the SNR and is used in many high-performance systems such as in the ADC for audio and DAT systems. This paper presents the design of the decimation and its VLSI implementation which is the sub-component in the oversampling technique. The design of three main units in the decimation stage that is the Cascaded Integrator Comb (CIC) filter, the associated half-band filters and the droop correction are also described. The Verilog HDL code in Xilinx ISE environment has been derived to describe the CIC filter properties and downloaded into Virtex II FPGA board. In the design of these units, we focus on the trade-off between the speed improvement and the power consumption as well as the silicon area for the chip implementation.
An Overview of the Decimation process and Its VLSI Implementation
Research Seminar SPS06. Faculty of Engineering, National University of Malaysia , pp. 207-211
Digital Decimation process plays an important task in a communication system. It mostly is applied in transceiver when the frequency reduction is required. However, the decimation process for sigma-delta modulator is considered in this research work. The proposed design was simulated using MATLAB software and implemented by hardware description language in Xilinx environment. Furthermore, the proposed advance arithmetic unit is applied to improve the system efficiency.
On-Chip Implementation of Cascaded Integrated Comb filters (CIC) for DSP applications
Research Student Seminar SPS05. Faculty of Engineering, National University of Malaysia , pp. 97-102.
This paper presents the design of CIC filters based on a low-pass filter for reducing the sampling rate, also known as decimation process. The targeted application for the filter is in the analog to digital conversion (ADC).The CIC is chosen because of its attractive property of both low power and complexity since it does not require multipliers. Simulink toolbox available in Matlab software is used to design and simulate the functionality of the CIC filter. This paper also shows how sample frequency is decreased by CIC filter and it can be used to give enough stop-band attenuation to prevent aliasing after decimation.
An Improved Recursive and Non-recursive Comb filter for DSP applications
Asian Control Conference. Institute Technology Bandung & IEEE Indonesia, 413-417
The recursive and non-recursive comb filters are commonly used as decimators for the sigma-delta modulators. This paper presents the analysis and design of low power and high-speed comb filters. The comparison is made between the recursive and the non-recursive comb filters with the focus on high speed and saving power consumption. Design procedures and examples are given by using Matlab and Verilog HDL for both recursive and non-recursive comb filter with emphasis on frequency response, transfer function and register width. The implementation results show that non-recursive comb filter has the capability of speeding up the circuit and reducing power compared to recursive one when the decimation ratio and filter order are high. Using Modified Carry Look-ahead Adder for summation and also apply pipelined filter structure makes it more compatible with DSP application.
VLSI Implementation of Cascaded Integrator comb filters for DSP applications
National Technical Postgraduate Symposium, TechPos 2006. Faculty of Engineering, University of Malaya, Malaysia, pp. 54-58.
The recursive comb filters or Cascaded Integrator Comb filter (CIC) are commonly used as decimators for the sigma-delta modulators. This paper presents the VLSI implementation, analysis and design of high-speed CIC filters which are based on a low-pass filter. These filters are used in the signal decimation which has the effect on reducing the sampling rate. It is also chosen because its attractive property of both low power and low complexity since it does not require a multiplier. Simulink toolbox available in Matlab software which is used to simulator and Verilog HDL coding help to verify the functionality of the CIC filters. Design procedures and examples are given for CIC filter with emphasis on frequency response, transfer function and register width. The implementation results show using Modified Carry Look-ahead Adder for summation and also apply pipelined filter structure enhanced high speed and make it more compatible with DSP applications.
Fourier Transforms - High-tech Application and Current Trends
ISBN 978-953-51-2894-6, DOI: 10.5772/66745, Chapter 4, Rozita Teymourzadeh, ISBN 978-953-51-2894-6, Print ISBN 978-953-51-2893-9, Published: February 8, 2017 under CC BY 3.0 license. © The Author(s).Intech Open Science Open Mind
Electrical motors are vital components of many industrial processes and their operation failure leads losing in the production line. Motor functionality and its behavior should be monitored to avoid production failure catastrophe. Hence, a high‐tech DSP processor is a significant method for electrical harmonic analysis that can be realized as embedded systems. This chapter introduces the principal embedded design of novel high‐tech 1024‐point FFT processor architecture for high-performance harmonic measurement techniques.
In FFT processor algorithm pipelining and parallel implementation is incorporated in order to enhance the performance. The proposed FFT makes use of floating point to realize higher precision FFT. Since floating‐point architecture limits the maximum clock
frequency and increases the power consumption, the chapter focuses on improving the speed, area, resolution and power consumption, as well as latency for the FFT. It illustrates very large‐scale integration (VLSI) implementation of the floating‐point parallel
pipelined (FPP) 1024‐point Radix II FFT processor with applying novel architecture that makes use of only single butterfly incorporation of intelligent controller. The functionality the conventional Radix II FFT was verified as embedded in FPGA prototyping. For area and power consumption, the proposed Radix II FPP‐FFT was optimized in ASIC under Silterra 0.18 μm and Mimos 0.35 μm technology libraries.